A chip built for the arithmetic of AI, such as a GPU. What is sold under the name is a small system (logic dies and stacks of high-bandwidth memory bonded into one package). Chapter 4.
From The AI Compute Race. Read the book
Where the book uses it
- Chapter 4 — One Rack
How a datacenter is actually built, from a converted factory in Memphis to a greenfield campus in Texas, and what the clock from first ground to first power really measures.
Where the record uses it
Sources that use it
- Northern States Power Company, doing business as Xcel Energy, “Petition of Northern States Power Company for Approval of Contracts for Provision of Electric Service to a New Large Customer Project,” Minnesota Public Utilities Commission, Docket No. E002/M-26-170, public version, eDockets document 20264-230408-02, 14 April 2026 (the utility’s petition for approval of its Electric Service Agreement with Echo Zone, LLC, “a subsidiary of Google LLC,” for facilities at Pine Island, Minnesota, the agreements contingent on the Commission’s approval, pp. 1 and 3; the electrical load the facilities “are anticipated to bring” and the Early Energization Target excised as trade secret, p. 3; “This ESA term is 15 years,” p. 6; the Exit Fee on a voluntary termination, “calculated by multiplying on-peak demand charges by 75 percent for the lesser of the remaining term or 96 months, as well as any remaining CEACs,” the Clean Energy Accelerator Charges, p. 14; every benefit figure in the petition is the utility’s own analysis; read in the public version, whose excisions are marked on every page; filed “Pursuant to Minn. Stat. § 216B.1622, subd. 2,” p. 1). In the Sources
- SemiAnalysis, “Engrams Embedding Entendre: Codesign for Efficient DRAM/SSD Offloading,” Bryan Shan, Cam Quilici, Alec Ibarra, Kimbo Chen, Myron Xie and Dylan Patel, 18 September 2026 (DeepSeek’s Engram architecture adds learned lookup tables that can be kept in a server’s host DRAM rather than in HBM: “With Engram model architecture optimization, it allows for lower HBM capacity to be needed for models at the same quality”; “This does not mean there won’t be an insane demand for HBM but it just means that model architecture will continue to innovate around constraints”; the relief is to capacity, not bandwidth, “When iso-model quality, less HBM is required as the engrams could be offloaded to host DRAM. Thus HBM bandwidth matters way more than HBM capacity”; everything cited here from the free portion of a paid post, held byte-exact in the Library since Sourcing’s capture of 24 September 2026) (SemiAnalysis sells subscriptions and consulting into the memory market it measures, and the post links its sentences on HBM to its own Memory model and Accelerator HBM model). In the Sources
Related terms
From the glossary of The AI Compute Race.
How to cite this page
Dryburgh, Lee S. “Accelerator.” In The AI Compute Race. DRYBURGH. https://dryburgh.com/vol1/glossary/accelerator (accessed 2026-11-01).
BibTeX
@misc{dryburgh-accelerator-2026,
author = {Dryburgh, Lee S.},
title = {{Accelerator}},
howpublished = {In \emph{The AI Compute Race}, DRYBURGH},
year = {2026},
url = {https://dryburgh.com/vol1/glossary/accelerator},
note = {Accessed 2026-11-01}
}